Driven by increased performance and high input/output (I/O) pin density, the paradigm of electronic packaging has shifted from perimeter-leaded packages to area array packages. For area array packages such as ball grid arrays (BGAs) and chip-scale packages (CSP), arrays of solder balls are attached to the bottom of a substrate. During assembly, packages are generally placed on circuit boards and processed using a reflow cycle, applied at a relatively high temperature that melts solder alloy. Typical reflow temperatures are approximately 220° C. for tin-lead (SnPb) eutectic alloy and 260° C. for lead-free tin-silver-copper (SAC) alloy with a composition Sn3.9Ag0.7Cu. Other temperatures may be suitable and other alloys, processed at suitable temperatures, may be used. Samples are cooled and the solder alloys hold the package in place.
One difficulty that may arise with conventional packages is that, since solder balls rigidly hold packages to the printed circuit boards, coefficient of thermal expansion (CTE) mismatch between the package and the printed circuit board may create thermo-mechanical stresses on the solder joint during temperature cycling, which may eventually cause solder joints to crack.
Another difficulty is that the solder joint is a permanent connection. During design, testing, and troubleshooting stages of product development, a capability to swap packages may be desirable to determine root causes of system failures or glitches. If packages are soldered to the printed circuit board, troubleshooting is highly difficult or impossible without removing the array packages.